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AX88180 asix electronics corporatio n released date: 5/18/2007 4f, no.8, hsin ann rd., hsinchu science park, hsinchu, taiwan, r.o.c. tel: 886-3-579-9500 fax: 886-3-579-9558 http://www.asix.com.tw high-performance non-pci 32-bit 10/100/1000m giga bit ethernet controller document no: AX88180/v1.4 features high-performance n on-pci local bus 16/32-bit sram- like host interface support big/little endian data bus type large embedded sram for packet buffers 32k bytes for receive buffer 8k bytes for transmit buffer support ip/tcp/udp checksum offloads support interrupt with high or low active trigger mode highly-integrated gigabit ethernet controller compatible with ieee802.3, 802.3u, and 802.3ab standards support 10/100/1000mbps data rate support full duplex operation with 1000mbps data rate support full and half duplex operations with 10/100mbps date rate support 10/100/1000mbps n-way auto-negotiation operation support ieee 802.3x flow control for full-duplex operation support 10/100/1000mbps data rate with rgmii or mii in 10/100mbps data rate. support back-pressure flow control for half-duplex operation support packet length set by software support max 4k bytes jumbo packet support wake-on-lan function by following events detection of network link-up state receipt of a magic packet support magic packet detection for remote wake-up after power?on reset support eeprom interface support pcmcia in 16-bit mode support synchronous or asynchronous mode to host mcu integrated voltage regulator from 3.3v to 2.5v 2.5v for core and 3.3v i/o with 5v tolerance 128-pin lqfp with cmos process, rohs package us patent approved (no 6799231) product description the AX88180 is a high-performance and cost-effective non-pci gigabit ethernet controller for various embedded systems including consumer electronics and home network markets that require a higher bandwidth of network connectivity. the AX88180 supports 16/32-bit sram-like host interface and gigabit ethernet mac, which is ieee802.3 10base-t, ieee802.3u 100base-t, and ieee 802.3ab 1000base-t compatible. the AX88180 supports full-duplex or half-duplex operation at 10/100/1000mbps speed with auto-negotiation or manual setting. the AX88180 integrates large embedded sram for packet buffers to accomm odate high bandwidth ap plications and supports ip/tcp/udp checksum to offload processing loading from microprocessor/microcontroller in an embedded system system block diagram always contact asix for possible updates before starting a design. this data sheet contains new produc ts information. asix electronics rese rves the rights to modify product specification without notice. no liability is assumed as a result of the use of this product. no rights under any patent accompany the sale of the product.
AX88180 2 asix electronics corporation target applications multimedia applications content distribution application audio distribution system (whole-house audio) video-over ip solutions, ip pbx and video phone video distribution system, multi-room pvr cable, satellite, and ip set-top box digital video recorder dvd recorder/player high definition tv digital media client/server home gateway iptv for triple play others printer, kiosk, security system wireless router & access point applications the AX88180, design with a high-performance risc cpu, provides a very low cost yet very high-performance embedded networking solution to enable easy and simple lan or inte rnet access capability to high-ba ndwidth multimedia application needs in the internet era.
AX88180 3 asix electronics corporation content 1.0 introduction............................................................................................................... .......................................................... 6 1.1 general description ........................................................................................................ ............................................... 6 1.2 AX88180 bl ock diagram...................................................................................................... ......................................... 6 1.3 AX88180 pino ut diagram..................................................................................................... ......................................... 7 2.0 signal description......................................................................................................... ...................................................... 8 2.1 signal type definition ..................................................................................................... .............................................. 8 2.2 rgmii/mi i interface ........................................................................................................ ............................................. 8 2.3 host interface............................................................................................................. .................................................... 9 2.4 eeprom interface ........................................................................................................... ........................................... 10 2.5 regulator interface........................................................................................................ ............................................... 10 2.6 miscellaneous .............................................................................................................. ................................................ 11 2.7 power/ground pin........................................................................................................... .............................................. 11 3.0 functional description..................................................................................................... ................................................. 12 3.1 host interface............................................................................................................. .................................................. 12 3.2 system ad dress range....................................................................................................... .......................................... 12 3.3 tx buffer operation ........................................................................................................ ............................................ 12 3.4 rx buffer operation........................................................................................................ ............................................ 12 3.5 flow control ............................................................................................................... ................................................. 13 3.6 checksum offloads and wake-up .............................................................................................. .................................. 13 3.7 burst-mode support ......................................................................................................... ............................................ 13 3.8 big/little-endi an support .................................................................................................. ........................................... 13 3.9 16-b it mo de................................................................................................................ .................................................. 13 3.10 eeprom format............................................................................................................. .......................................... 14 4.0 register descrip tion ....................................................................................................... .................................................. 15 4.1 cmd--command register ...................................................................................................... ..................................... 16 4.2 imr--interrupt mask re gister ............................................................................................... ...................................... 16 4.3 isr--interrupt status register............................................................................................. ......................................... 17 4.4 tx_cfg--tx configuration register .......................................................................................... ............................... 18 4.5 tx_cmd--tx command register ................................................................................................ ............................. 18 4.6 txbs--tx buffer status register ............................................................................................ ................................... 18 4.7 txdes0--tx descriptor0 register............................................................................................ ................................. 19 4.8 txdes1--tx descriptor1 register............................................................................................ ................................. 19 4.9 txdes2--tx descriptor2 register............................................................................................ ................................. 20 4.10 txdes3--tx de scriptor3 register........................................................................................... ................................ 20 4.11 rx_cfg--rx conf iguration register......................................................................................... .............................. 20 4.12 rxcurt--rx current pointer register ....................................................................................... ............................. 21 4.13 rxbound--rx bound ary pointer register ..................................................................................... ....................... 21 4.14 mac_cfg0--mac conf iguration0 register..................................................................................... ....................... 21 4.15 mac_cfg1--mac conf iguration1 register..................................................................................... ....................... 21 4.16 mac_cfg2--mac conf iguration2 register..................................................................................... ....................... 22 4.17 mac_cfg3--mac conf iguration3 register..................................................................................... ....................... 23 4.18 txpaut--tx pause time register ............................................................................................ ............................... 23 4.19 rxbthd0--rx buffer threshold0 register .................................................................................... ......................... 23 4.20 rxbthd1--rx buffer threshold1 register .................................................................................... ........................ 23 4.21 rxfulthd--rx buffer full threshold register............................................................................... ...................... 24 4.22 misc?misc. control re gister ............................................................................................... .................................. 24 4.23 macid0--mac id0 re gister .................................................................................................. ................................. 24 4.24 macid1--mac id1 re gister .................................................................................................. ................................. 24 4.25 macid2--mac id2 re gister .................................................................................................. ................................. 25 4.26 txlen--tx length register ................................................................................................. ................................... 25 4.27 rxfilter--rx pack et filter register ....................................................................................... .............................. 25 4.28 mdioctrl--mdio control re gister ........................................................................................... ........................... 26 4.29 mdiodp--mdio da ta port register ........................................................................................... ............................. 26 4.30 gpio_ctrl--gpi o control register.......................................................................................... ............................. 26
AX88180 4 asix electronics corporation 4.31 rxindicator--receiv e indicator register................................................................................... ......................... 27 4.32 txst--tx status register .................................................................................................. ....................................... 27 4.33 mdclkpat--mdc cl ock pattern regist er ...................................................................................... ........................ 27 4.34 rxchksumcnt--rx ip/udp /tcp checksum error counter......................................................................... ...... 27 4.35 rxcrcnt--rx crc error counter............................................................................................. ............................ 28 4.36 txfailcnt--tx fail counter ................................................................................................ ................................. 28 4.37 promdpr--eeprom data port register ........................................................................................ ....................... 28 4.38 promctrl--eepro m control register ......................................................................................... ....................... 28 4.39 maxrxlen--max. rx packet lengt h register.................................................................................. .................... 29 4.40 hashtab0--hash table0 register ............................................................................................ .............................. 29 4.41 hashtab1--hash table1 register ............................................................................................ .............................. 29 4.42 hashtab2--hash table2 register ............................................................................................ .............................. 29 4.43 hashtab3--hash table3 register ............................................................................................ .............................. 29 4.44 dogthd0?watch dog ti mer threshold0 register ............................................................................... ................ 30 4.45 dogthd1?watch dog ti mer threshold1 register ............................................................................... ................ 30 4.46 softrst --- soft ware reset register ....................................................................................... ............................... 30 5.0 electrical specifi cation and timings ....................................................................................... ......................................... 31 5.1 dc charac teris tics ......................................................................................................... .............................................. 31 5.1.1 absolute maximum ratings................................................................................................. ................................. 31 5.1.2 general operation conditions ............................................................................................. ................................ 31 5.1.3 leakage current and capacitance.......................................................................................... ............................. 31 5.1.4 dc characteristic s of 2.5v io pins ....................................................................................... .............................. 31 5.1.5 dc characteristic s of 3.3v io pins ....................................................................................... .............................. 32 5.1.6 power consumption ........................................................................................................ ..................................... 32 5.1.7 thermal characteristics.................................................................................................. ..................................... 32 5.2 a.c. timing characteristics ................................................................................................ ......................................... 33 5.2.1 host clock ............................................................................................................... ............................................. 33 5.2.2 reset timing ............................................................................................................. ............................................ 33 5.2.3 host single write timing................................................................................................. ..................................... 33 5.2.4 host burst write timing .................................................................................................. ..................................... 34 5.2.5 host single read timing .................................................................................................. .................................... 34 5.2.6 host burst read timing................................................................................................... ..................................... 35 5.2.7 rgmii clock timing ....................................................................................................... ..................................... 35 5.2.8 rgmii receive timing (1000/100/10 mbps).................................................................................. ...................... 36 5.2.9 rgmii transmit timing .................................................................................................... ................................... 36 5.2.10 mdio timing ............................................................................................................. ........................................ 37 5.2.11 serial eeprom timing.................................................................................................... .................................. 37 6.0 package information ........................................................................................................ ................................................. 38 7.0 ordering information....................................................................................................... ................................................. 39 appendix a1. 16-bit mode addres s and data bus............................................................................................... ................ 40 appendix a2. 32-bit mode addres s and data bus............................................................................................... ................ 42 appendix a3. AX88180 with giga -phy connection............................................................................................... ........ 43 appendix a4. synchronous and asynchro nous timing selection.................................................................................. ..... 44 appendix a5. wake on lan (wol) without driver via ma gic packet........................................................................... 45
AX88180 5 asix electronics corporation revision history ............................................................................................................... ...................................................... 46 list of figures figure 1 : AX88180 block diagram ............................................................................................... ....................................... 6 figure 2 : AX88180 pi n connection diagram...................................................................................... .................................. 7 figure 3: 32-bit m ode address mapping.......................................................................................... ...................................... 12 figure 4: data swap block ...................................................................................................... ............................................... 13 figure 5: 16-bit m ode memory mapping ........................................................................................... ................................... 14 list of tables table 1 : rgmii/mii inte rface signal s group .................................................................................... ....................................... 8 table 2 : host inte rface signal s group ......................................................................................... ............................................. 9 table 3 : eeprom interf ace signal s group....................................................................................... ..................................... 10 table 4 : regulato r signals group .............................................................................................. ............................................. 10 table 5 : miscellane ous signals group .......................................................................................... .......................................... 11 table 6 : power/grou nd pins group .............................................................................................. .......................................... 11 table 7: mac re gister mapping.................................................................................................. .......................................... 15
AX88180 6 asix electronics corporation 1.0 introduction 1.1 general description the AX88180, sram-like 16/32-bit local bus to gigabit ethernet bridge, supports a 10/100/1000 mbps with rgmii (v2.0 in delay timing) or mii in wire-speed operation. AX88180 supports rgmii (802.3ab, 1000base-t) interface with full-duplex operation at gigabit speed and full-duplex or half-duplex operation at 10/100 mbps speed. AX88180 can also operate in mii mode with 10/100mbps speed. the AX88180 has two built-in synchronous sram for bufferi ng packet. the one is 32k bytes for receiving packets from ethernet phy; the other is 8k-bytes for transmitting packets from host system to ethernet phy. the AX88180 also has 256 bytes built-in configuration regist ers. for software programming, the tota l address space used in AX88180 is 64k in 32-bit mode and at least (8k + 8) bytes in 16-bit mode. because AX88180 is a sram-like device, AX88180 could be treated as a sram device and can be attached to sram controller of system. therefore, system can execu te dma cycles to gain the highest performance. AX88180 needs 2 clock sources. one (hclk) is the same to host system clock or from stand-along osc, the other is 125mhz (clk125) for AX88180 running in rgmii mode. in general application, the 125mhz clock can be from giga -phy for cost effectively. 1.2 AX88180 block diagram figure 1 : AX88180 block diagram
AX88180 7 asix electronics corporation 1.3 AX88180 pinout diagram the AX88180 is housed in the 128-pin lqfp package. gnd 87 rxdv 70 vcc25 4 txd2 62 ha14 22 hd27 112 hd20 122 vcc25 107 ha9 28 hd14 2 ha1 42 vcc25 89 test5 90 vcc33 13 vcc33 119 gnd 82 hd29 110 txd0 65 hclk 104 vcc33 40 v25out 38 hd21 121 vcc25 117 ha7 30 test3 84 hd7 11 gtxclk 67 hd31 108 hd9 9 hd19 124 eedo 50 gnd 101 nc 93 hd26 113 vcc33 1 test6 97 hd1 18 crs 79 vcc25 72 hd18 125 hd10 7 eedi 49 test0 52 hd8 10 ha3 34 mdio 59 gnd 92 rxd0 74 nc 94 gpio0 55 vcc25 60 intn 102 hd15 128 hd17 126 hd5 14 gnd 99 rxd2 76 gndr 36 eeclk 47 hd25 114 ha11 25 vcc25 57 txd1 63 vcc25 123 gnd 86 txclk 69 hd2 17 hd4 15 hd16 127 wen 44 hd12 5 vcc25 20 vcc33r 37 non-pci 16 / 32 bit gigabit ethernet controller test4 88 ha2 41 hd28 111 rxclk 71 vcc25 96 ha6 31 hd13 3 ha8 29 ha15 21 vcc25 81 vcc25 100 reg_en 39 oen 43 gnd 106 vcc25 98 hd3 16 hd22 120 test2 83 ha12 24 hd23 118 txen 66 vcc25 85 nc 91 csn 45 hd30 109 vcc25 27 AX88180 wakeup 115 vcc25 78 gnd 8 ha10 26 clk125 51 ha4 33 col 80 gnd 73 gpio1 54 hd11 6 test1 53 txd3 61 hd0 19 hd24 116 vcc25 35 phyintn 46 rst_n 103 rxd1 75 ha13 23 gnd 56 vcc33 105 rxd3 77 vcc25 64 eecs 48 txcx 68 gnd 95 hd6 12 ha5 32 mdc 58 figure 2 : AX88180 pin connection diagram
AX88180 8 asix electronics corporation 2.0 signal description 2.1 signal type definition i3: input, 3.3v with 5v tolerance i2: input, 2.5v with 3.3v tolerance i25 input 2.5v only o3: output, 3.3v o2: output, 2.5v io3: input/output, input 3.3v with 5v tolerance io2: input/output, input 2.5v with 3.3v tolerance tso: tri-state output od: open drain allows multiple devices to share as a wire-or pd: internal 75k pull down pu: internal 75k pull up gnd: digital ground vcc3: 3.3v power vcc2: 2.5v power i: input only o: output only io: input/output 2.2 rgmii/mii interface table 1 : rgmii/mii interface signals group pin name type pin no pin description clk125 i3 51 free running clock 125mhz from osc or giga-phy. txen o2, 12ma 66 transmit enable: txen is transition synchronously with respect to the rising and falling edge o f txcx. txen indicates that the port is presenting nibbles on txd [3:0] for transmission. txd[3:0] o2, 12ma 61,62,63,65 transmit data: txd[3:0] is transition synchronously with respect to the rising and falling edge o f txcx. in rising edge txd[3:0] is as general td[3:0] and falling edge txd[3:0] is as td[7:4]. td[7:0] is us ed in AX88180 as byte unit. txcx o2, 12ma 68 125mhz clock output: it is a continuous 125 mhz clock output to giga-phy operating in rgmii mode. it is a timing reference for txen and txd[3: 0]. for normal operation, this pin will be connected to giga-phy. gtxclk o2, 12ma 67 125mhz clock output: it is a continuous 125 mhz clock output. this pin is for internal debug purpose only and should be floating for normal operation. rxclk i2 71 receive clock: rxclk is a continuous clock that provides the timing reference for rxdv, rxd[3:0]. this clock is provided from phy. rxd[3:0] i2 77,76,75,74 receive data: rxd[3:0] is driven by the phy synchronously with respect to rxclk. in rising edge rxd[3:0] is as rd[3:0] and falling edge is as rd[7:4]. rd[7:0] is used in AX88180 as byte unit. rxdv i2 70 receive data valid: rxdv is driven by the phy synchronously with respect to rxclk in rising and falling edge. it is asserted high when valid data is present on rxd [3:0]. col i2 80 collision: this signal is driven by phy when collision is detected. crs i2 79 carrier sense:
AX88180 9 asix electronics corporation asynchronous signal crs is asserted by the phy when either the transmitted or receive medium is non-idle. mdio io2, pu, 8ma 59 station management data input /output: serial data input/output transfers from/to the phy. the transfer protocol conforms to the ieee 802.3u mii specification. mdc o2, 8ma 58 station management data clock: the timing reference for mdio. all data tr ansfers on mdio are synchronized to the rising edge of this clock. phyintn i2 46 interrupt signal from phy, active low. txclk i2 69 a clock from giga-phy operates in mii mode. if giga-phy provides clock for 10/100m in mii mode, AX88180 can use this pin as reference clock. for normal operation, to connect txclk of giga-phy with this pin. 2.3 host interface table 2 : host interface signals group pin name type pin no pin description intn tso, 8ma 102 interrupt to host system when the polarity is active high, this signal must be pulled low, otherwise pulled high in active low environment. software set the bit6 of command register (cmd) to response the polarity. rst_n i3 103 reset signal: active low. hclk i3 104 reference clock. this clock may be from host (synchronous mode) or the output of stand-alone osc (asynchronous mode). wakeup tso, 8ma 115 wake-up signal to system. when the polarity of system is active high, this signal must be pulled low, otherwise pulled high in active low environment. software set the bit0 of command register (cmd) to response the polarity. hd0 io3, 8ma 19 data bus bit0. hd1 io3, 8ma 18 data bus bit1. hd2 io3, 8ma 17 data bus bit2. hd3 io3, 8ma 16 data bus bit3. hd4 io3, 8ma 15 data bus bit4. hd5 io3, 8ma 14 data bus bit5. hd6 io3, 8ma 12 data bus bit6. hd7 io3, 8ma 11 data bus bit7. hd8 io3, 8ma 10 data bus bit8. hd9 io3, 8ma 9 data bus bit9. hd10 io3, 8ma 7 data bus bit10. hd11 io3, 8ma 6 data bus bit11. hd12 io3, 8ma 5 data bus bit12. hd13 io3, 8ma 3 data bus bit13. hd14 io3, 8ma 2 data bus bit14. hd15 io3, 8ma 128 data bus bit15. hd16 io3, 8ma 127 data bus bit16, internal pull down. * hd17 io3, 8ma 126 data bus bit17, internal pull down. * hd18 io3, 8ma 125 data bus bit18, internal pull down. * hd19 io3, 8ma 124 data bus bit19, internal pull down. * hd20 io3, 8ma 122 data bus bit20, internal pull down. * hd21 io3, 8ma 121 data bus bit21, internal pull down. * hd22 io3, 8ma 120 data bus bit22, internal pull down. * hd23 io3, 8ma 118 data bus bit23, internal pull down. * hd24 io3, 8ma 116 data bus bit24, internal pull down. * hd25 io3, 8ma 114 data bus bit25, internal pull down. *
AX88180 10 asix electronics corporation hd26 io3, 8ma 113 data bus bit26, internal pull down. * hd27 io3, 8ma 112 data bus bit27, internal pull down. * hd28 io3, 8ma 111 data bus bit28, internal pull down. * hd29 io3, 8ma 110 data bus bit29, internal pull down. * hd30 io3, 8ma 109 data bus bit30, internal pull down. * hd31 io3, 8ma 108 data bus bit31, internal pull down. * ha1 i3 42 address bus bit1. ha2 i3 41 address bus bit2. ha3 i3 34 address bus bit3. ha4 i3 33 address bus bit4. ha5 i3 32 address bus bit5. ha6 i3 31 address bus bit6. ha7 i3 30 address bus bit7. ha8 i3 29 address bus bit8. ha9 i3 28 address bus bit9. ha10 i3 26 address bus bit10. ha11 i3 25 address bus bit11. ha12 i3 24 address bus bit12. ha13 i3 23 address bus bit13. ha14 i3 22 address bus bit14. ha15 i3 21 address bus bit15. wen i3 44 data write enable: host drives wen and it is active low. csn i3 45 chip select enable. host drives csn and it is active low. oen i3 43 data output enable: host drives oen and it is active low. *note: the internal pull-down of hd16 to hd31 will be disabled in 32-bit mode. 2.4 eeprom interface table 3 : eeprom interface signals group pin name type pin no. pin description eeclk o3, 12ma 47 a low speed clock to eeprom eecs o3, 12ma 48 chip select to eeprom device. eedi o3, 12ma 49 data to eeprom, valid in eecs is high and eeclk in rising edge. eedo i3, pd 50 data from eeprom 2.5 regulator interface table 4 : regulator signals group pin name type pin no. pin description vcc33r vcc3 37 3.3v power to internal regulator gndr gnd 36 ground pin for internal regulator reg_en i3 39 high to enable internal regulator. low to disable internal regulator. v25out o2 38 2.5v output from internal regulator, max 250ma, when reg_en pin is high.
AX88180 11 asix electronics corporation 2.6 miscellaneous table 5 : miscellaneous signals group pin name type pin no. pin description gpio0 io3, 12ma, pd 55 general purpose pin. in reset stage this pin defines chip operates in 16 or 32- b it mode. pull-down is for 32-bit mode and pull-up (by 4.7k) is for 16- b it mode. if this pin is floating, it will be as default for 32-bit mode. gpio1 io3, 12ma, pd 54 general purpose pin. in reset stage this pin defines chip operates in little-endian or big-endian mode. pull-down is little-endian mode and pull-up is big-endian mode. i f this pin is floating, it will as default for little-endian mode. test0 i3, pd 52 connect to ground for normal operation. test1 i3, pd 53 connect to ground for normal operation. test2 i25 83 connect to ground for normal operation. test3 i25 84 connect to ground for normal operation. test4 i25 88 pull-down for normal operation test5 i25 90 connect to ground for normal operation. test6 i25 97 pull-up (with 4.7k) for normal operation nc o 91,93,94 no connection 2.7 power/ground pin table 6 : power/ground pins group pin name type pin no. pin description vcc33 vcc3 1,13,40, 105, 119 3.3v power pins vcc25 vcc2 4,20,27,35,57,60,64,72,78,81,85,89,96,98,100,107, 117,123 2.5v power pins gnd gnd 8,56,73,82,86,87,92,95,99,101,106 ground pins
AX88180 12 asix electronics corporation 3.0 functional description 3.1 host interface AX88180 supports a very simple sram-lik e interface. there are only 3 control si gnals to operate the read or write. for write operation, host activates csn and wen to low with address and data bus. AX88180 will decode and latched the data into internal buffer. for normal operation, the wen needs at least 4 clocks duration for one 32/16-bit write operation. the csn can always be driven, but wen must at least be de-asserted 1 clock before next access. for read operation, host asserts csn and oen at least 5 clocks to AX88180, the data will be valid after 4 clocks. AX88180 also support burst mode if host reads/writes AX88180 by continuous access. note: the burst mode only supports in tx/rx, not supports in registers read/write. that is, reads rx area from xxxx _0000 to xxxx_7fff or writes tx area from xxxx_8000 to xxxx_fbff can be accessed by burst mechanism. 3.2 system address range AX88180 is suitable to attach to sr am controller, so it needs 64k memory space for operation. the designer can allocate any block (64k) in system space. from offset 0x0000 to 0x7fff is for rx operation, and offset 0x8000 to 0xfbff is for tx operation. the internal configuration register of AX88180 is allocated in offset 0xfc00 to 0xfcff. below is the mapping of addressing. figure 3: 32-bit mode address mapping 3.3 tx buffer operation AX88180 employs 4 descriptors to maintain transmit informat ion, such as packet length, start bit. these descriptors are located in offset 0xfc20, 0xfc24, 0xfc28 and 0xfc2c. driver can choose any descriptor whenever there is data needed to be transmitted. since there are only 4 descriptors, upon running out of descriptors, driver must wait for the descriptor is to be released by AX88180. 3.4 rx buffer operation AX88180 is built a 32k sram for rx operation. it utilizes ring structure to maintain the input data from phy and read out to host. there are two pointer registers located in offset 0xfc34 and oxfc38. AX88180 will maintain rxcurt register. upon it receives a valid packet from phy it will update rxcurt accordin g to the packet length. driver reads data from AX88180 and maintains the rxbound register. when driver finishes reading packet, it must update rxbound according to the packet length. AX88180 utilizes rxcurt and rxbound to provide receive buffer status, full or empty. r x area 32768 bytes xxxx_ 0000h xxxx _8000h xxxx_fc00h 31 0 t x area 31744 bytes r egisters area 256 bytes xxxx_fd00h n o used area 768 bytes xxxx_ffffh
AX88180 13 asix electronics corporation 3.5 flow control in full duplex mode, AX88180 su pports the standard flow control mechanis m defined in ieee 802.3x standard. it enables the stopping of remote node tr ansmissions via a pause frame information interaction. when space of the packet buffer is less than the threshold values (rxbthd0, rxbthd 1), AX88180 will send out a pause-on packet to stop the remote node transmission. and then ax881 80 will send out a pause-off packet to inform the remote node to retransmit packet if it has enough space to receive packets. 3.6 checksum offloads and wake-up to reduce the computing loading of cpu, AX88180 is built checksum operator for ip, udp or tcp packet. AX88180 will detect the packet whether it is ip, udp or tcp packet. if it is an ip packet, AX88180 will calculate the checksum of header and put the result in checksum filed of ip. then it continuously checks the packet whether it is udp or tcp. it will perform the checksum operation whenever it is a udp or tcp packet. AX88180 also automatically skip the vlan tag when checksum is executed. AX88180 also supports to detect magic packet or lin k-up to wake up system when system is in sleep state or needs to cold start by magic packet. 3.7 burst-mode support to improve the throughput in embedded system, AX88180 supports fast-mode (burst) for tx/rx buffer access. host can access AX88180 by driving csn to low and toggle wen (write ) or oen (read). AX88180 can support the burst until whole packet access. the access timing can refer to section 5. 2.4 and 5.2.6. this mechanis m is only for tx/rx buffer access. for configuration register access, it must use single access. 3.8 big/little-endian support AX88180 supports ?big? or ?little? endian data format. th e default is little-endian. designer can pull-up goio1 pin to high to swap the data format. below table can depict the relation. this swap is only valid in 32-bit mode. figure 4: data swap block 3.9 16-bit mode AX88180 also supports 16-bit mode ope ration. AX88180 driver should request at least (8k + 8) bytes space for tx, rx and register access. for example, the dr iver requests a 16k bytes space from syst em and then sets the new window base address to membas6 register. after that, driver should set bit 0 (decode_en) of membase register to start decoding for tx buffer, rx buffer and registers access. (note: AX88180 h/w only decodes lo w 16-bit offset address.) membase--memory base address field name type default description 15:1 - r/w - reserved. the output value is undefined if software read this field. 0 decode_en r/w 0 16-bit decode enable set to ?1? to start decoding. membas6--memory base address + 6 field name type default description 15:8 - r/w - reserved. the output value is undefined if software read this field. 7:0 winsize r/w 0x00 window base pointer. (the msb of new window base address, 16-bit offset) this field defines another new windows base address for tx, rx and register access. the total size is 8k bytes. tx areas occupy 3840 bytes registers occupy 256 bytes. rx areas occupy 4096 bytes. note: the winsize field of this address is used to define the msb of new window base address, the tx buffer, rx buffer and registers should be accessed through this new window base address in 16-bit mode. please refer to below mapping mechanism for details. little-endian d[31:24] d[23:16] d[15:8] d[7:0] d[7:0] d[15:0] d[23:16] d[31:24] big-endian
AX88180 14 asix electronics corporation membase set membas6 = 0x0010 tx buffer area (3840 bytes) registers area (256 bytes) rx buffer area (4096 bytes) figure 5: 16-bit mode memory mapping the following is an example to indicate how to define a new window base address in 16-bit mode by configuring the membas6 register. if AX88180 is allocated at the memory base address 0x20_0000 by hardware (i.e. the membase register is allocated at 0x20_0000) and users would like to set the new window base address to 0x20_1000, the driver should write 0x0010 to the membas6 register (offset 0x20_0006) . in this case, the tx buffer area will be allocated from 0x20_1000 to 0x20_1eff; the registers area will be allocated from 0x20_1f00 to 0x20_1fff and the rx buffer area will be allocated from 0x20_2000 to 0x20_2fff. (note: AX88180 only decodes low 16-bit address) 3.10 eeprom format AX88180 will auto-load data from eeprom device after hard ware reset. if the eeprom device is not attached, the loading operation will be discarded. the eeprom mainly prov ides mac address information and cis information if it is used in pcmcia environment. below table is the format if eeprom device is employed. no te: if the mac address is 12 34 56 78 9a bc (msb-lsb) then driver should set macid0=0x9abc, macid1=0x5678 and macid2=0x1234. address 16-bits data description 0 pointer to starting address of cis area. set this fiel d to 0x0070 to shorten the download eeprom if there is no cis needed. AX88180 only supports the 16-bit mode of 93c56, thus the max value of this field is 0x007f. this field should not be set to 0x0000 or 0xffff; otherwise, AX88180 will not recognize the eeprom during hardware reset. 1 macid0 data 2 macid1 data 3 macid2 data 4 reserved, keep all 0?s 5 bit0: when gpio0 is set to ?1? in reset stage, this bit indicates AX88180 whether it is in the environment of pcmcia. 0 = general 16-bit mode, 1= special for pcmcia environment of 16-bit mode. bit1: must be ?0? bit2: 1 = set rgmii mode by eeprom, 0 = none. (the setting will be cleared when software resets) bit3: 1 = set gigabit mode by eeprom, 0=none (t he setting will be cleared when software resets) others bits must set to 0s 6 ~ 11 reserved, keep all 0?s 12 ~ 127 cis area, if AX88180 is used in pc mcia system, otherwise set them to all ?0s? 15 0 registers area (xx_1f00 ~ 1fff) rx buffer area (xx_2000 ~ 2fff) base address (xx_0000) n ew window base address (xx_ 10 00) tx buffer area (xx_1000 ~ 1eff) base address + 6 (xx_0006)
AX88180 15 asix electronics corporation 4.0 register description there are some registers located from 0x fc00 to 0xfcff. all of the registers ar e 32-bit boundary alignment, but only low 16-bit are available (exception 0xfc54). for reserved bits, don?t set them in normal operation. table 7: mac register mapping offset name description default value 0xfc00 cmd command register 0x0000_0201 0xfc04 imr interrupt mask register 0x0000_0000 0xfc08 isr interrupt status register 0x0000_0000 0xfc10 tx_cfg tx configuration register 0x0000_0040 0xfc14 tx_cmd tx command register 0x0000_0000 0xfc18 txbs tx buffer status register 0x0000_0000 0xfc20 txdes0 tx descriptor0 register 0x0000_0000 0xfc24 txdes1 tx descriptor1 register 0x0000_0000 0xfc28 txdes2 tx descriptor2 register 0x0000_0000 0xfc2c txdes3 tx descriptor3 register 0x0000_0000 0xfc30 rx_cfg rx configuration register 0x0000_0101 0xfc34 rxcurt rx current pointer register 0x0000_0000 0xfc38 rxbound rx boundary pointer register 0x0000_07ff 0xfc40 mac_cfg0 mac configuration0 register 0x0000_8157 0xfc44 mac_cfg1 mac configuration1 register 0x0000_6000 0xfc48 mac_cfg2 mac configuration2 register 0x0000_0100 0xfc4c mac_cfg3 mac configuration3 register 0x0000_060e 0xfc54 txpaut tx pause time register 0x001f_e000 0xfc58 rxbthd0 rx buffer threshold0 register 0x0000_0300 0xfc5c rxbthd1 rx buffer threshold1 register 0x0000_0600 0xfc60 rxfulthd rx buffer full threshold register 0x0000_0100 0xfc68 misc misc. control register 0x0000_0013 0xfc70 macid0 mac id0 register * 0x0000_0000 0xfc74 macid1 mac id1 register * 0x0000_0000 0xfc78 macid2 mac id2 register * 0x0000_0000 0xfc7c txlen tx length register 0x0000_05fc 0xfc80 rxfilter rx packet filter register 0x0000_0004 0xfc84 mdioctrl mdio control register 0x0000_0000 0xfc88 mdiodp mdio data port register 0x0000_0000 0xfc8c gpio_ctrl gpio control register * 0x0000_0003 0xfc90 rxindicator receive i ndicator register 0x0000_0000 0xfc94 txst tx status register 0x0000_0000 0xfca0 mdclkpat mdc clock pattern register 0x0000_8040 0xfca4 rxchksumcnt rx ip/udp/tcp checksum error counter 0x0000_0000 0xfca8 rxcrcnt rx crc error counter 0x0000_0000 0xfcac txfailcnt tx fail counter 0x0000_0000 0xfcb0 promdpr eeprom data port register 0x0000_0000 0xfcb4 promctrl eeprom control register 0x0000_0000 0xfcb8 maxrxlen max. rx packet length register 0x0000_0600 0xfcc0 hashtab0 hash table0 register * 0x0000_0000 0xfcc4 hashtab1 hash table1 register * 0x0000_0000 0xfcc8 hashtab2 hash table2 register * 0x0000_0000 0xfccc hashtab3 hash table3 register * 0x0000_0000 0xfce0 dogthd0 watch dog timer threshold0 register 0x0000_ffff 0xfce4 dogthd1 watch dog timer threshold1 register 0x0000_0000 0xfcec softrst software reset register 0x0000_0003 *note: it is not affected by software reset
AX88180 16 asix electronics corporation 4.1 cmd--command register offset address = 0xfc00 default = 0x0000_0201 field name type default description 31:16 - r/w all 0?s reserved 15 rxvlan r/w 0 rx vlan indicator driver enables this bit to indicate AX88180 that the recei ved packet will include 4 bytes vlan tag; AX88180 will skip 4 bytes when it calculates the checksum of ip, tcp or udp packet. 1 = enable 0 = disable 14 txvlan r/w 0 tx vlan indicator driver enables this bit to indicate AX88180 that the transmitted packet will include 4 bytes vlan tag; AX88180 will skip 4 bytes when it calculates the checksum of ip, tcp or udp packet. 1 = enable 0 = disable 13:10 - r/w all 0?s reserved 9 rxen r/w 1 rx function enable when this bit is enabled, mac starts to receive packets. 1 = enable 0 = disable 8 txen r/w 0 tx function enable when this bit is enabled, mac could start to transmit packet to ethernet. 1 = enable 0 = disable 7 - r/w 0 reserved 6 intmod r/w 0 interrupt active mode driver sets this bit to indicate AX88180 the interrupt of system is activated high or low. 1: active high 0: active low 5:1 - r/w all 0?s reserved 0 wakemod r/w 1 wakeup pin polarity driver sets this bit to indicate AX88180 the polarity of system wake-up signal is activated high or low. 1: active high 0: active low 4.2 imr--interrupt mask register offset address = 0xfc04 default = 0x0000_0000 field name type default description 31:6 - r all 0?s reserved 5 phymask r/w 0 phy interrupt mask when this bit is enabled, an interr upt request from phy set in bit 5 of interrupt status register will make AX88180 to issue an interrupt to host. 1 = enable 0 = disable 4 prim r/w 0 packet recei ved interrupt mask when this bit is enabled, a received interrupt request set in bit 4 of interrupt status register will make AX88180 to issue an interrupt to host. 1 = enable 0 = disable 3 ptim r/w 0 packet transmitted interrupt mask when this bit is enabled, a transmitted interrupt request set in bit 3 of interrupt status register will make AX88180 issue an interrupt to host.
AX88180 17 asix electronics corporation 1 = enable 0 = disable 2 - r/w 0 reserved 1 dogim r/w 0 watch dog timer interrupt mask when this bit is enabled, a watch dog timer expired interrupt request set in bit1 of interrupt status register will make AX88180 to issue an interrupt to host 1 = enable 0 = disable 0 rxfulim r/w 0 rx buffer full interrupt mask when this bit is enabled, a rx buffer full interrupt request set in bit 0 of interrupt status register will make AX88180 to issue an interrupt to host. 1 = enable 0 = disable 4.3 isr--interrupt status register offset address = 0xfc08 default = 0x0000_0000 field name type default description 31:6 - r all 0?s reserved 5 phyig r/w 0 phy interrupt generation if this bit is set to ?1?, it means there is an interrupt request from phy. AX88180 will forward this interrupt to system. meantime driver should poll phy and adopt proper procedure. write ?1? to this bit to clear this request status. 1 = have interrupt request 0 = no interrupt request 4 rpig r/w 0 receive packet interrupt generation if this bit is set to ?1?, it means ax88 180 receives a packet or (packets) from phy. the packet is kept in rx buffer. write ?1? to this bit to clear this request status. 1 = have received packet 0 = no received packet 3 ftpi r/w 0 finish transmitting packet interrupt if this bit is set to ?1?, it means ax881 80 had transmitted packet to phy. write ?1? to this bit to clear this request status. 1 = finish transmission 0 = none 2 - r/w 0 reserved 1 wdtei r/w 0 watch dog timer expired interrupt if this bit is set to ?1?, it means the watch dog timer is expired. AX88180 will issue an interrupt to host. write ?1? to this bit to clear this request status. the expired duration can refer to dogthd0 and dogthd1 registers. 1 = timer expired happens 0 = none 0 rxfuli r/w 0 rx buffer full interrupt if this bit is set to ?1? it means rx buffer is full and no more packets will be received until packets are read out. write ?1? to this bit to clear this request status. 1 = rx buffer full 0 = none
AX88180 18 asix electronics corporation 4.4 tx_cfg--tx configuration register offset address = 0xfc10 default = 0x0000_0040 field name type default description 31:7 - r all 0?s reserved 6 txcrcap r/w 1 txcrc auto-append when this bit is enabled, AX88180 will append crc to the transmitted packet in fcs field. 1 = enable 0 = disable 5 - r/w 0 reserved. 4 txchksum r/w 0 tx checksum generation when this bit is enabled, AX88180 will append checksum to the transmitted packet that is ip or tcp or udp packet. 1 = enable 0 = disable 3:2 - r 00 reserved 1:0 txds r 00 tx description status AX88180 reports which descriptor is transmitted now default: 2?b00 4.5 tx_cmd--tx command register offset address = 0xfc14 default = 0x0000_0000 field name type default description 31:16 - r all 0?s reserved 15 hwi r/w 0 host writes indication before host begins to send a packet to tx buffer, this bit should be set. at the end of host writes the packet, this bit should be cleared by software. 1 = start writing 0 = end writing 14:13 txdp r/w 00 tx descriptor pointer to specify which tx descriptor to be written. 12 - r/w 0 reserved 11:0 datalen r/w all 0?s byte count. data length is written to transmitted buffer. 4.6 txbs--tx buffer status register offset address = 0xfc18 default = 0x0000_0000 field name type default description 31:4 - r all 0?s reserved 8 intxds r 0 internal tx descriptor status. this bit reports the tx descriptor status. when there is data to be transmitted, this bit will be set to ?1? otherwise it will be ?0? 1 = have data in tx buffer 0 = all data are transmitted to phy 7:6 - r 00 reserved 5:4 txduse r 00 tx descriptor in transmitting these status bits indicate which descriptor is transmitting now. 00: descriptor 0 in transmitting 01: descriptor 1 in transmitting 10: descriptor 2 in transmitting 11: descriptor 3 in transmitting 3 txd3o r/w 0 tx descriptor 3 occupied driver set this bit to ?1? to indicate that it had used tx descriptor3. when the
AX88180 19 asix electronics corporation transmission is finished, AX88180 will auto-clear this bit. 2 txd2o r/w 0 tx descriptor 2 occupied driver set this bit to ?1? to indicate that it had used tx descriptor2. when the transmission is finished, AX88180 will auto-clear this bit. 1 txd1o r/w 0 tx descriptor 1 occupied driver set this bit to ?1? to indicate that it had used tx descriptor1. when the transmission is finished, AX88180 will auto-clear this bit. 0 txd0o r/w 0 tx descriptor 0 occupied driver set this bit to ?1? to indicate that it had used tx descriptor0. when the transmission is finished, AX88180 will auto-clear this bit. 4.7 txdes0--tx descriptor0 register offset address = 0xfc20 default = 0x0000_0000 field name type default description 31:16 - r all 0?s reserved 15 txd0_en r/w 0 transmit tx descriptor 0 if this bit is enabled, mac will begin to transmit data that are stored in tx buffer. in former, driver had already written data that is assigned to tx descriptor0 to tx buffer. this bit will be cleared by hardware when mac finished the transmission. 1= enable 0= disable 14:13 - r 00 reserved 12:0 txd0_len r/w all 0?s tx packet length (unit: byte) driver set this field to indicate AX88180 how many bytes will be transmitted. 4.8 txdes1--tx descriptor1 register offset address = 0xfc24 default = 0x0000_0000 field name type default description 31:16 - r all 0?s reserved 15 txd1_en r/w 0 transmit tx descriptor 1 if this bit is enabled, mac will begin to transmit data that are stored in tx b uffer. in former, driver had already written data that is assigned to tx descriptor1 to tx buffer. this bit will be cleared by hardware when mac finished the transmission. 1= enable 0= disable 14:13 - r 00 reserved 12:0 txd1_len r/w all 0?s tx packet length (unit: byte) driver set this field to indicate AX88180 how many bytes will be transmitted.
AX88180 20 asix electronics corporation 4.9 txdes2--tx descriptor2 register offset address = 0xfc28 default = 0x0000_0000 field name type default description 31:16 - r all 0?s reserved 15 txd2_en r/w 0 transmit tx descriptor 2 if this bit is enabled, mac will begin to transmit data that are stored in tx buffer. in former, driver had already written data that is assigned to tx descriptor2 to tx buffer. this bit will be cleared by hardware when mac finished the transmission. 1= enable 0= disable 14:13 - r 00 reserved 12:0 txd2_len r/w all 0?s tx packet length (unit: byte) driver set this field to indicate AX88180 how many bytes will be transmitted. 4.10 txdes3--tx descriptor3 register offset address = 0xfc2c default = 0x0000_0000 field name type default description 31:16 - r all 0?s reserved 15 txd3_en r/w 0 transmit tx descriptor 3 if this bit is enabled, mac will begin to transmit data that are stored in tx b uffer. in former, driver had already written data that is assigned to tx descriptor3 to tx buffer. this bit will be cleared by hardware when mac finished the transmission. 1= enable 0= disable 14:13 - r 00 reserved 12:0 txd3_len r/w all 0?s tx packet length (unit: byte) driver set this field to indicate AX88180 how many bytes will be transmitted. 4.11 rx_cfg--rx configuration register offset address = 0xfc30 default = 0x0000_0101 field name type default description 31:9 - r all 0?s reserved 8 rxbme r/w 1 rx buffer monitor enable when this bit is enabled, mac will monitor the status of receive buffer. 1 = enable 0 = disable 7:5 - r/w 000 reserved. 4 rxchksum r/w 0 rx pa cket tcp/ip checksum when this bit is set, AX88180 will check the ch ecksum of the received packet that is ip, tcp or udp packet. if there is checksum error, AX88180 will drop the packet and rxchksumcnt counter will add 1. 1 = enable 0 = disable 3:1 - r/w 000 reserved 0 rxbufpro r/w 1 rx buffer protection when this bit is enabled, mac will protect the rx buffer to avoid overrun. for normal operation, this bit should be enabled in initial stage. 1= enable 0= disable
AX88180 21 asix electronics corporation 4.12 rxcurt--rx current pointer register offset address = 0xfc34 default = 0x0000_0000 field name type default description 31:11 - r all 0?s reserved 10:0 rxcurptr r/w all 0?s rx line current pointer. point to the last line that will be wr itten by hardware. the unit of line is 16 bytes. AX88180 will maintain this register. 4.13 rxbound--rx boundary pointer register offset address = 0xfc38 default = 0x0000_07ff field name type default description 31:11 - r all 0?s reserved 10:0 rxbunptr r/w 0x7ff rx line boundary pointer. point to the last line that has been read by driver. the unit of line is 16 bytes. when driver finished reading packet from rx buffer, it must update this field. 4.14 mac_cfg0--mac configuration0 register offset address = 0xfc40 default = 0x0000_8157 field name type default description 31:16 - r all 0?s reserved 15 speed100 r/w 1 line speed mode when this bit is enabled and bit12 of mac_cfg1 is disabled, mac will operate in 100mbps mode otherwise it operates in 10mbps speed. if bit12 of mac_cfg1 is enabled, this bit will be ignored 14 - r/w 0 reserved, this bit must set to 0 for normal operation 13 - r/w 0 reserved, this bit must set to 0 for normal operation. 12 rxflow r/w 0 rx flow control if this bit and bit8 of rx_cfg ar e enabled, mac will perform flow control and send pause on/off frame when the available space of receive buffer is less than the value of rxbthd0. 1 = enable 0 = disable 11 - r/w 0 reserved, this bit must set to 0 for normal operation. 10:4 ipg100 r/w 0x15 inter packet gap (ipg) for 10/100m this field defines the back-to-back transmit packet gap for 10/100m. 3:0 ipg1000 r/w 0x7 inter packet gap for 1000m this field defines the back-to-back transmit packet gap for 1000m only. 4.15 mac_cfg1--mac configuration1 register offset address = 0xfc44 default = 0x0000_6000 field name type default description 31:15 - r all 0?s reserved 14 pusrule r/w 1 pause frame check rule when this bit is set, AX88180 accept s pause frame that da can be any value. 1 = don?t check da field. 0 = check da is equal to ?01 80 c2 00 00 01? 13 crcchk r/w 1 check crc of received packet. when this bit is enabled, AX88180 will drop any crc error packet.
AX88180 22 asix electronics corporation 1 = enable 0 = disable 12 giga_en r/w 0 gigabit mode enable when this bit is enabled, mac will operate in 1000mbps mode. 1 = enable 0 = disable 11 rxjumbo r/w 0 rx jumbo enable when this bit is enabled, mac will receive jumbo package 1 = enable 0 = disable 10:7 rxjubolen r/w 0000 length limit of received jumbo package this field defines the maximum length of received jumbo package. 0001: 1k bytes 0010: 2k bytes 0011: 3k bytes --------------------- 1110: 14k bytes 1111: 15k bytes 6 duplex r/w 0 duplex mode. 1 = full-duplex mode 0 = half-duplex mode 5 txflw_en r/w 0 tx flow enable when this bit is enabled, mac will block the transmitted operation when it captures pause frame from ethernet. the re-transmission will be activated until the waiting time is expired. 1 = enable 0 = disable 4:2 - r/w 000 reserved, must set to ?0s? for normal operation 1 rgmiien r/w 0 rgmii mode enable when this bit is enabled, AX88180 w ill operate in rgmii interface. driver must set external phy to rgmii mode and enable this bit in initial stage. driver also must set rgmii interface of external phy with add-delay timing in its internal. 1 = enable 0 = disable 0 - r/w 0 reserved, must set to ?0s? for normal operation 4.16 mac_cfg2--mac configuration2 register offset address = 0xfc48 default = 0x0000_0100 field name type default description 15:8 - r/w 0x01 reserved, keep this field in default value for normal operation. 7:2 jamlt r/w 000000 define jam limit for backpressure collision account. normally set this field at 0x19. it can avoid hub port going to partition state due to too many collisions. AX88180 will skip one frame collision backpressure when collision counter equal to jamlt. the collision count will be reset to zero when every transmit frame with no collision or receive a frame with no backpressure collision. 1:0 - r/w 00 reserved, must set to ?00? for normal operation
AX88180 23 asix electronics corporation 4.17 mac_cfg3--mac configuration3 register offset address = 0xfc4c default = 0x0000_060e field name type default description 15 noabort r/w 0 no abort when this bit is enabled, mac will keep retry transmit current frame even excessive collision otherwise it will abort current transmission due to excessive collision. 1 = enable 0 = disable 13:7 ipgr1 r/w 0001100 inter-frame gap segment1 6:0 ipgr2 r/w 0001110 inter-frame gap segment2 4.18 txpaut--tx pause time register offset address= 0xfc54 default = 0x001f_e000 field name type default description 31:23 - r all 0?s reserved 22:0 txpval r/w 0x1f_e000 tx pause time out it is used to re-transmit a pause-on frame when pause timer expired and receive buffer still not enough. in 32-bit mode, this field should be set to 0x1f_e000 at 1000mbps mode and set to 0x7f_8000 at 10/100mbps modes. in 16-bit mode, this field should be set to 0xffff at 10/100/1000mbps modes. (note: the bit 16 ~ 22 of this field are invalid in 16-bit mode.) 4.19 rxbthd0--rx buffer threshold0 register offset address= 0xfc58 default = 0x0000_0300 field name type default description 31:11 - r all 0?s reserved 10:0 rxlowb r/w 0x300 rx remainder capacity low-bound this field defines as the remainder capacity of rx buffer for pause operation. if the flow control (bit12 of mac_cfg0) is enabled, mac will send pause frame when the available space of receive buffer is less than this value. the unit is 16-byte. 4.20 rxbthd1--rx buffer threshold1 register offset address= 0xfc5c default = 0x0000_0600 field name type default description 31:11 - r all 0?s reserved 10:0 rxhighb r/w 0x600 rx remainder capacity upper-bound this field defines as upper bound of remainder size of rx buffer for pause operation. if the flow control is enabled, mac will stop to send pause frame until the available space of receive buffer is more than this value. the unit is 16-byte.
AX88180 24 asix electronics corporation 4.21 rxfulthd--rx buffer full threshold register offset address= 0xfc60 default = 0x0000_0100 field name type default description 31:11 - r all 0?s reserved 10:0 rxfulb r/w 0x100 rx full threshold this field defines the least capacity of rx buffer. AX88180 will cause rx full if it remains capacity under this value. the unit is 16-byte. 4.22 misc?misc. control register offset address= 0xfc68 default = 0x0000_0013 field name type default description 31:6 - r all 0?s reserved 5 wake_lnk r/w 0 wake-up by link-up function if this bit is enabled, mac will drive wakeup pin whenever there is link-up occurrence. the polarity of wakeup pin is according to bit0 of cmd register. 1= enable 0= disable 4 wake_mag r/w 1 wake-up by magic packet if this bit is enabled, mac will driv e wakeup pin whenever there is magic p acket detected by hardware. the polarity of wakeup pin is according to bit0 of cmd register. 1= enable wake-up by magic packet 0 = disable 3:2 - r/w 00 reserved 1 - r/w 1 reserved 0 srst_mac r/w 1 software reset mac core driver set this bit to ?0? to reset core of mac. the reset duration is depended on whenever this bit is de-asserted by driver. there are only rxcurt and rxbound registers will be cleared by this bit. others registers will not be affected 1 = in normal operation 0 = in reset status 4.23 macid0--mac id0 register offset address = 0xfc70 default = 0x0000_0000 field name type default description 31:16 - r all 0?s reserved. 15:0 mid15_0 r/w 0x0000 mac id address [15:0]. this field defines lower address bit15 to bit0 of mac. the macid0, macid1 and macid2 comb ine into 48- b it mac address. the mac address format is [47:0] = {macid2[15:0], macid1[15:0], macid0[15:0]}. if the eeprom is attached, this field will be auto-loaded from eeprom after hardware reset. 4.24 macid1--mac id1 register offset address = 0xfc74h default = 0x0000_0000 field name type default description 31:16 - r all 0?s reserved. 15:0 mid31_16 r/w 0x0000 mac id address [31:16].
AX88180 25 asix electronics corporation 4.25 macid2--mac id2 register offset address = 0xfc78 default = 0x0000_0000 field name type default description 31:16 - r all 0?s reserved. 15:0 mid47_32 r/w 0x0000 mac id address [47:32]. 4.26 txlen--tx length register offset address = 0xfc7c default = 0x0000_05fc field name type default description 31:11 - r all 0?s reserved 10:0 maxtxlen r/w 0x5fc max tx packet size this field defines the maximum raw packet size in transmittance. it is not included 4 bytes crc. 4.27 rxfilter--rx packet filter register offset address = 0xfc80 default = 0x0000_0004 field name type default description 31:6 - r all 0?s reserved 5 goodcrc r/w 0 good crc enable when this bit is enabled, AX88180 will receive any packet of good crc. 1 = enable 0 = disable 4 multi_hash r/w 0 receive multicast packet by lookup hash table . when this is enabled, AX88180 w ill receive multicast packet by the hash mapping function. it will refer to hastab0, hashtab1, hashtab2 and hashtab3 to look up the table. 1 = enable 0 = disable 3 broadcast r/w 0 receive broadcast packet when this bit is enabled, AX88180 will receive the broadcast packet 1 = enable 0 = disable 2 unicast r/w 1 receive directed packet. if this bit is enabled, AX88180 will compare the destination address field of received packet with the address of mac (refer to macid0, macid1, macid2). when it is matched and good crc, the packet will be passed to driver. otherwise it will be dropped. 1 = enable 0 = disable 1 multicast r/w 0 receive all multicast packets. if this bit is enabled, any multicast packet (good crc) will b e received and passed to driver. 1 = enable 0 = disable 0 rxany r/w 0 receive anything. if this bit is enabled, any packet whether it is good or fail will be received and passed to driver. 1 = enable 0 = disable
AX88180 26 asix electronics corporation 4.28 mdioctrl--mdio control register offset address = 0xfc84 default = 0x0000_0000 field name type default description 31:16 - r all 0?s reserved 15 wten r/w 0 write enable. driver enables this bit to issue a write cy cle to phy, it will be auto-cleared when AX88180 finishes the write cycle 1 = enable 0 = disable 14 rden r/w 0 read enable. driver enables this bit to issue a read cy cle to phy. this bit will be auto-cleared when AX88180 finishes the read cycle 1 = enable 0 = disable 12:8 phycridx r/w 00000 phy register index driver sets this field to define the inte rnal register index of phy when it accesses phy. 7:5 - r 000 reserved 4:0 phyid r/w 00000 phy id driver sets the phy id value in this fiel d. AX88180 will refer to this field when it accesses phy by mdio/mdc signals. 4.29 mdiodp--mdio data port register offset address = 0xfc88 default = 0x0000_0000 field name type default description 31:16 - r all 0?s reserved 15:0 mdport r/w all 0?s phy data port to or from phy data is put in this field. 4.30 gpio_ctrl--gpio control register offset address = 0xfc8c default = 0x0000_0003 field name type default description 31:10 - r all 0?s reserved 9 gpio1s r/w 0 gpio1 status this bit stands for the pin status of gpio1 when it is set to input mode. 1 = high state 0 = low state 8 gpio0s r/w 0 gpio0 status this bit stands for the pin status of gpio0 when it is set to input mode. 1 = high state 0 = low state 7:2 - r all 0?s reserved 1 gpio1dir r/w 1 gpio1 mode direction this field defines the direction of gpio1 pin. 1 = input mode 0 = output mode 0 gpio0dir r/w 1 gpio0 mode direction this field defines the direction of gpio pin. 1 = input mode 0 = output mode note: for output mode, software must firstly set the bit0 or bit1 to output mode then set bit8 or bit9.
AX88180 27 asix electronics corporation 4.31 rxindicator--receive indicator register offset address= 0xfc90 default = 0x0000_0000 field name type default description 31:1 - r all 0?s reserved 0 rxstart r/w 0 receive start driver sets this bit to st art or end receive operation fr om rx buffer of AX88180. 1= start read rx buffer 0= end read rx buffer 4.32 txst--tx status register offset address = 0xfc94 default = 0x0000_0000 field name type default description 31:4 - r all 0?s reserved 3 txd3fail r 0 tx descriptor3 transmit fail when this bit is set 1, it means AX88180 fails in transmission of descriptor3. this bit will be self-cleared when driver reads txst register. 2 txd2fail r 0 tx descriptor2 transmit fail when this bit is set 1, it means a88180 fails in transmission of descriptor2. this bit will be self-cleared when driver reads txst register. 1 txd1fail r 0 tx descriptor1 transmit fail when this bit is set 1, it means AX88180 fails in transmission of descriptor1. this bit will be self-cleared when driver reads txst register. 0 txd0fail r 0 tx descriptor0 transmit fail when this bit is set 1, it means AX88180 fails in transmission of descriptor0. this bit will be self-cleared when driver reads txst register. 4.33 mdclkpat--mdc clock pattern register offset address = 0xfca0 default = 0x0000_8040 field name type default description 31:16 - r all 0?s reserved 15:8 - r/w 0x80 reserved, must set to 0x80 for normal operation 7:0 mdcpat r/w 0x40 mdc clock divide factor this field defines the divided factor of host clock. AX88180 will refer to this field and generate a low speed clock to phy. 4.34 rxchksumcnt--rx ip/udp/tcp checksum error counter offset address = 0xfca4 default = 0x0000_0000 field name type default description 31:16 - r all 0?s reserved 15:0 rxchkercnt r/w all 0?s rx checksum error counter if the rxchksum field of rx_cfg regist er is set to ?1?, mac will check the checksum of ip, tcp or udp packet. whenever there is checksum error detected, this field will be added one. the value will be rounded back to 0x0000 if it exceeds 0xffff.
AX88180 28 asix electronics corporation 4.35 rxcrcnt--rx crc error counter offset address = 0xfca8 default = 0x0000_0000 field name type default description 31:16 - r all 0?s reserved 15:0 rxcrccnt r/w all 0?s rx crc32 error counter mac checks the received packet. if there is a crc error detect, this field will be added one. the value will be rounde d back to 0x0000 if it exceeds 0xffff. 4.36 txfailcnt--tx fail counter offset address = 0xfcac default = 0x0000_0000 field name type default description 31:16 - r all 0?s reserved 15:0 txfilcnt r/w all 0?s tx fail counter this field records the number of transm itted error for tx packet. the value will be rounded back to 0x0000 if it exceeds 0xffff. 4.37 promdpr--eeprom data port register offset address = 0xfcb0 default = 0x0000_0000 field name type default description 31:16 - r all 0?s reserved 15:0 promdp r/w all 0?s eeprom data port the data to or from eeprom is set in this field. 4.38 promctrl--eeprom control register offset address= 0xfcb4 default = 0x0000_0000 field name type default description 31:15 - r all 0?s reserved 14:12 rom_cmd r/w 000 eeprom command code. driver set this field to represent what type command will be send to eeprom device. 110 = read command 111 = erase command 101 = write command 11 rom_wt r/w 0 write eeprom set to ?1? to write eeprom, it will be auto-cleared when AX88180 finishes the write operation. 10 rom_rd r/w 0 read eeprom set to ?1? to read eeprom, it will be cleared when mac finished the read operation. driver can read promdpr register to get the returned data. 9 rom_rld r/w 0 reload eeprom set to ?1? to re-load eeprom, this bit will be auto-cleared when AX88180 finishes loading operation. 8 - r 0 reserved 7:0 rom_addr r/w 0x00 eeprom address set this field to define the address for serial eeprom access. (only support 16-bit data access, e.g. 93c56 type)
AX88180 29 asix electronics corporation 4.39 maxrxlen--max. rx packet length register offset address= 0xfcb8 default = 0x0000_0600 field name type default description 31:11 - r all 0?s reserved 10:0 rxlen r/w 0x600 max rx packet length this field defines the max length of recei ved packet. it doesn?t include 4-byte crc. 4.40 hashtab0--hash table0 register offset address = 0xfcc0 default = 0x0000_0000 field name type default description 31:16 - r all 0?s reserved 15:0 htab0 r/w 0x0000 hash table: bit15~bit0 driver sets hashtab0, hashtab1, hashtab2 and hashtab3 to define 64- b it hash table. AX88180 will refer this table to check multicast packet if multicast filter is enabled (bit4 of rxfilter) for rx. when AX88180 receives a packet then it extracts the destination address (da). the da is calculated by crc32 algorithm. after the operation, AX88180 will grab the msb[31:27] of result as hash table index. the range of index is from 0 to 63. for example, the hash table is composite as {hashtab3[15:0], hashtab2[15:0], hashtab1[15:0], hashtab0[15:0]}. if AX88180 detects the msb[31:27] = 26 of crc32 of da for someone multicast packet, and driver set ?1? to hashtab1[10], then the multicast packet will received by AX88180. 4.41 hashtab1--hash table1 register offset address = 0xfcc4 default = 0x0000_0000 field name type default description 31:16 - r all 0?s reserved 15:0 htab1 r/w 0x0000 hash table: bit31~bit16 4.42 hashtab2--hash table2 register offset address = 0xfcc8 default = 0x0000_0000 field name type default description 31:16 - r all 0?s reserved 15:0 htab2 r/w 0x0000 hash table: bit47~bit32 4.43 hashtab3--hash table3 register offset address = 0xfccc default = 0x0000_0000 field name type default description 31:16 - r all 0?s reserved 15:0 htab3 r/w 0x0000 hash table: bit63 ~ bit48
AX88180 30 asix electronics corporation 4.44 dogthd0?watch dog timer threshold0 register offset address = 0xfce0 default = 0x0000_ffff field name type default description 31:16 - r all 0?s reserved 15:0 dogth0 r/w 0xffff watch dog timer low word this register and dogthd1[11:0] are defined to an expired threshold for internal watchdog counter. the threshold {[dogthd1, dogthd0] is a 28- b it value. to multiply 28-bit value with one-cycle period of a host clock is the expired duration. if the dogen is set to ?1? and wdtei of isr is set, then AX88180 will periodically generate interrupt whenever the counter reaches to the threshold. 4.45 dogthd1?watch dog timer threshold1 register address = 0xfce4 default = 0x0000_0000 field name type default description 31:16 - r all 0?s reserved 15 dogen r/w 0 dog timer enable 1 = enable internal dog timer 0 = disable 14:12 - r/w all 0?s reserved 11:0 dogth1 r/w 0x000 dog timer high field. this field and dogthd0[15:0] combine to a 28-bit register. 4.46 softrst --- software reset register address = 0xfcec default = 0x0000_0003 field name type default description 31:2 - r all 0?s reserved 1 - r/w 1 reserved 0 rst_mac r/w 1 software reset enable driver set this bit to ?0? to reset mac. the reset duration is depended on whenever this bit is de-asserted by driver . most registers will be cleared to default value. 1 = in normal operation 0 = in reset status
AX88180 31 asix electronics corporation 5.0 electrical specification and timings 5.1 dc characteristics 5.1.1 absolute maximum ratings symbol description rating units t stg storage temperature -40 to 150 c vcc3 power supply of 3.3v -0.3 to vcc3 + 0.3 v vcc2 power supply of 2.5v -0.3 to vcc2 + 0.3 v v i3 input voltage of 3.3v io with 5v tolerance -0.3 to 5.5 v v i2 input voltage of 2.5v io with 3.3v tolerance -0.3 to 3.9 v note: stress above those listed under absolute maximum ratings may cause permanent damage to the device. exposure to absolute maximum ratings conditions for extended pe riod, adversely affect device life and reliability. 5.1.2 general operation conditions symbol description min typ max units tj junction temperature 0 - 115 c vcc2 supply voltage of 2.5v 2.25 2.5 2.75 v vcc3 supply voltage of 3.3v 3.0 3.3 3.6 v v i3 input voltage of 3.3v io with 5v tolerance 0 3.3 5.25 v v i2 input voltage of 2.5v io with 3.3v tolerance 0 2.5 3.6 v 5.1.3 leakage current and capacitance symbol description min typ max units i in input leakage current -10 1 +10 a i oz tri-state leakage current -10 1 +10 a c out output capacitance - 3.1 - pf c bid bi-directional buffer capacitance - 3.1 - pf 5.1.4 dc characteristics of 2.5v io pins symbol description min typ max units vcc2 power supply of 2.5v io 2.25 2.5 2.75 v vil input low voltage - - 0.7 v vih input high voltage 1.7 - - v vol output low voltage - - 0.4 v voh output high voltage 1.85 v rpu input pull-up resistance 40 75 190 k rpd input pull-down resistance 40 75 190 k
AX88180 32 asix electronics corporation 5.1.5 dc characteristics of 3.3v io pins symbol description min typ max units vcc3 power supply of 3.3v io 3.0 3.3 3.6 v vil input low voltage - - 0.8 v vih input high voltage 2.0 - - v vol output low voltage - - 0.4 v voh output high voltage 2.4 v rpu input pull-up resistance 40 75 190 k rpd input pull-down resistance 40 75 190 k 5.1.6 power consumption device only measurement bases on 100mhz frequency of hclk and turn on internal regulator at 25 o c temperature. item symbol power-on with cable removed operation at 10base-t operation at 100base-t operation at 1000base-t stand-by current (hclk is off) units 1 vcc3 (io) 1.6 1.8 2.4 2.5 0.061 ma 2 vcc3r 87 72 79 105 1.5 ma note: the current of vcc3r in cludes vcc2 core current. 5.1.7 thermal characteristics a. junction to ambient thermal resistance, ja symbol min typ max units ja - 46.3 - o c/w b. junction to case thermal resistance, jc symbol min typ max units jc - 16.2 o c/w note: ja , jc defined as below ja = p t t a j ? , jc = p t t c j ? t j : maximum junction temperature t a : ambient or environment temperature t c : the top center of com pound surface temperature p: input power (watts)
AX88180 33 asix electronics corporation 5.2 a.c. timing characteristics 5.2.1 host clock a. reference clock (hclk) description min typ. max units reference frequency 40 - 100 mhz reference clock duty cycle 40 50 60 % b. reference clock (clk125) description min typ. max units reference frequency - 125 - mhz reference clock duty cycle 45 50 55 % 5.2.2 reset timing symbol description min typ. max units trst reset pulse width 0.5 - - ms 5.2.3 host single write timing symbol description min typ. max units tsetup csn, wen to hclk setup timing 2 - - ns tar ha exceed to wen timing 0 hclk tad ha exceed to wen timing 0 hclk tvalid_cycle a valid write cycle timing (synchronous to mcu) 4 - - hclk tvalid_cycle a valid write cycle timing- (asynchronous to mcu) 6 - - hclk hclk rst_n trst hclk csn wen valid address ha[15:1] valid data hd[31:0] tsetup tar tad tvalid_cycle
AX88180 34 asix electronics corporation 5.2.4 host burst write timing symbol description min typ. max units twen valid write cycle timing 6 - - hclk 5.2.5 host single read timing symbol description min typ. max units tac csn/oen access timing (synchronous to mcu) 5 - - hclk tac csn/oen access timing (asynchronous to mcu) 6 hclk tovd oen assert to valid data timing 4 - - hclk tdh valid data hold timing to oen de-asserted 0 ns hclk csn ha[15:1] wen address address + 4 address + 8 twen valid data valid data valid data twen hclk csn/oen valid data valid address ha[15:1] hd[31:0] tac tovd tdh
AX88180 35 asix electronics corporation 5.2.6 host burst read timing symbol description min typ. max units tac valid address access timing 6 hclk tovd oen assert to valid data timing 4 - - hclk tad burst mode address to valid data 4 hclk tdh valid data hold timing to oen de-asserted 0 ns 5.2.7 rgmii clock timing symbol description min typ. max units tcycle-1000 cycle timing for 1000base-t 7.2 8 8.8 ns thi-1000 high timing for 1000base-t 3.6 4 4.4 ns tlo--1000 low timing for 1000base-t 3.6 4 4.4 ns tcycle -100 cycle timing for 100base-t 32 40 44 ns thi-100 high timing for 100base-t 16 20 22 ns tlo-100 low timing for 100base-t 16 20 22 ns tcycle -10 cycle timing for 10base-t 320 400 440 ns thi-10 high timing for 10base-t 160 200 220 ns tlo-10 low timing for 100base-t 160 200 220 ns trising rising timing - 0.8 - ns tfall fall timing - 0.8 - ns thi tlo tcycle trising tfall hclk csn oen valid data (a1) valid data (a2) valid data (a3) address (a1) address + 4 (a2) invalid data address + 8 (a3) tovd tad tad tdh tac tac tac
AX88180 36 asix electronics corporation 5.2.8 rgmii receive timing (1000/100/10 mbps) symbol description min typ. max units tsetup setup timing to rxclk (at AX88180) 1.0 - - ns thold hold timing to rxclk (at AX88180) 1.0 - - ns note: phy adds the de lay in rxclk 5.2.9 rgmii transmit timing symbol description min typ. max units tskew data to clock txcx skew -500 0 +500 ps tdelay data to clock in phy site 1.5 2.0 ns note: phy needs to add delay in txcx rxd[3:0] rxdv rxclk (at AX88180) tsetup thold tx d [3:0] txen tx c x (at a x 88180 ) t x c x (at p h y internal) tskew tdelay tdealy
AX88180 37 asix electronics corporation 5.2.10 mdio timing symbol description min typ. max units tclk mdc clock timing* 1340 - ns tod mdc falling edge to mdio output delay - 32 ns ts mdio data input setup timing 10 - - ns th mdio data input hold timing 4 - - ns 5.2.11 serial eeprom timing symbol description min typ. max units tclk eeclk clock timing* 1370 - ns tod eeclk falling edge to ee di output delay - 5 ns ts eedo data input setup timing 6 - - ns th eedo data input hold timing 6 - - ns tscs eecs output valid to eeclk rising edge 650 ns thcs eeclk falling edge to eecs invalid timing 0 ns tlcs minimum eecs low timing - 560 - ns mdio (output) mdc tc lk mdio ( inp ut) ts th tod eedi (output) eeclk tclk eedo (input) ts th tod eecs tlcs thcs tscs
AX88180 38 asix electronics corporation 6.0 package information b e d hd e he pin 1 a2 a1 l l1 a milimeter symbol min. nom max a1 0.05 0.1 a2 1.35 1.4 1.45 a 1.6 b 0.13 0.18 0.23 d 13.90 14.00 14.10 e 13.90 14.00 14.10 e 0.40 hd 15.85 16.00 16.15 he 15.85 16.00 16.15 l 0.45 0.60 0.75 l1 1.00 0 7
AX88180 39 asix electronics corporation 7.0 ordering information AX88180 l f product name package lqfp f: lead free
AX88180 40 asix electronics corporation appendix a1. 16-bit mode address and data bus a1-1. 16-bit mode and separated address and data bus note: the name of control signal for mcu is demonstrated only. a1-1-1. AX88180 is synchronous to host mcu a1-1-2. AX88180 is asynchronous to host mcu note: for asynchronous mode, system must provide extra osc to output clock to AX88180 csn /c s x /r d o e n /w r w e n clk hclk a[15:1] ha[15:1] d[15:0] hd[15:0] /intx intn /reset rst_n 3.3v generic m cu AX88180 hd[31:16] gpio0 n ote: floating 4.7k csn /c s x /r d o e n /w r w e n hclk a [15:1] ha[15:1] d [15:0] hd[15:0] /in t x in t n /reset rst_n 3.3v g eneric m cu a x 88180 h d [31:16] gpio0 n o te: flo atin g osc 4.7k
AX88180 41 asix electronics corporation a1-2. 16-bit mode multiplexed address and data csn /c s x /r d o e n /w r w e n bclk hclk ad[15:0] ha[15:1] hd[15:0] /in t x in t n /reset rst_n AX88180 hd[31:16] ale addr[15:1] latch 3.3v gpio0 n ote: f loating 4.7k
AX88180 42 asix electronics corporation appendix a2. 32-bit mode address and data bus a2-1. linear address mode and byte aligned (in synchronous mode) note: for asynchronous mode, system must provide extra osc to output clock to AX88180. please refer to section a1-1-2 for details. a2-2. mcu is double-word boundary a nd the addressing is dword unit csn /c s x /r d o e n /w r w e n clk hclk a[13:0] ha[15:2] d[31:0] hd[31:0] /in t x in t n /reset rst_n generic m cu AX88180 gpio0 floating, if no use ground ha1 csn /c s x /r d o e n /w r w e n clk hclk a[15:1] ha[15:1] d[31:0] hd[31:0] /intx intn /reset rst_n generic m cu AX88180 gpio0 floating, if no use
AX88180 43 asix electronics corporation appendix a3. AX88180 with giga-phy connection AX88180 giga-phy rxd[3:0] rxd[3:0] rx d v rx_dv rxclk rx_clk col col crs crs mdio mdio mdc mdc in t n phyintn txd[3:0] txd[3:0] tx e n tx _ e n tx c lk tx _ c lk txcx gtx_clk 125clk clk125 gtxclk 88e1111 giga-m ac
AX88180 44 asix electronics corporation appendix a4. synchronous and asynchronous timing selection AX88180 can support sy nchronous or asynch ronous access from host mcu. be low information provides some references to select clock frequency of host mcu and AX88180. a4-1. AX88180 is synchronous with host mcu. the timing selection is suitable for both 32-bit and 16-bit mode. frequency access type valid access timing (oen/wen active timing) max 100mhz single or burst min 5 clocks a4-2. AX88180 is asynchronous to host mcu. the timing selection is suitable for both 32-bit and 16-bit mode. frequency access type valid access timing (oen/wen active timing) max 100mhz single or burst min 6 reference clocks (note) note: the reference clock is from osc, and it?s not the output of host mcu. for instance, if AX88180 runs in asynchronous mode and refers a 100mhz clock from osc, whereas mcu runs in 125mhz environment. in such condition, mcu must at least offer 60ns (min 6 reference clock of 100mhz) access timing to AX88180. the 60ns for mcu is almost reached to 8 clocks (125mhz). we recommend that it is needed to extend the access timing of mcu to AX88180.
AX88180 45 asix electronics corporation appendix a5. wake on lan (wol) without driver via magic packet a5-1. wake on lan (wol) without driver AX88180 can support wol without driver exists. in su ch situations, system must offer 3.3v voltage, reference clock and rest signal to AX88180. wh enever AX88180 detects magic pa cket from cable, it will drive wakeup signal to host system. AX88180 defaults in mi i interface (after reset before eeprom auto-loaded). hence if giga-phy supports rgmii inte rface, designer must use eeprom to set AX88180 to rgmii interface. users must take care is that AX88180 only supports delay timing of rgmii (refer to 5.2.8), thus it must add extra delay (at least 0.7ns) in pcb board if system needs wol and without running driver. below diagram is shown the concept. another available method is to set giga-phy in mii mode (by configure pin, if giga-phy has this feature). after AX88180 detects magic packet and wakes up system, driver can set AX88180 to rgmii mode and also set giga-phy to rgmii mode by mdio in terface. if designer employs this ap proach, the delay ti ming issue is not needed. a5-2. magic packet the magic packet received by AX88180 is shown as following; da + sa + 0x0000 + 0xffffffffffff + (at least repeats 16 times) da + crc32 da = mac address of AX88180 (6 bytes) sa = source address (6 bytes) mcu osc hclk power rc circuit or reset pulse generator data addr csn/oen/wen delay line rxclk rxclk AX88180 giga-phy no power area rst_n
AX88180 46 asix electronics corporation revision history revision date comment v1.0 2005/10/4 first edition v1.0a 2006/3/31 1. correct so me typos in section 3.4. 2. correct the name definition of some pins in section 1-3 and section 2. v1.1 2006/7/28 1. some typo errors corrected between pin diagram and tables. 2. host read/write timing revised in section 5. 3. some bits of registers are updated. 4. add some connections between mcu and AX88180 in appendix. 5. add wake up lan in appendix. 6. update the power consumption information in section 5.1.6. v1.2 2007/3/28 1. correct some information in section 3.9 for 16-bit mode operation. 2. modify the data access timing inform ation in section 5.2.5, 5.2.6 and appendix a4. 3. update the power consumption information in section 5.1.6. 4. add some information in section 3.10. 5. define the bit filed name (rxjubolen) for bit 10:7 of mac_cfg1 register. 6. add AX88180 with gigabit phy connection information in appendix a3. 7. modify some descriptions in section 1.1, 4.6, 4.16, 4.17, 4.18, 4.22, 4.34~4.36, 4.40. 8. modify the description of txclk and gtxclk pin in section 2.2. 9. rearrange the content of appendix into appendix a1~a5. 10. change the number format from 16h?xxxx to 0xxxxx for example. v1.3 2007/5/4 1. swap the pin definition of pin #90 and #91 in section 2.6 and figure 2. 2 . correct some typo errors of pin type in table 1 and table 5. v1.4 2007/5/18 1. modify max operation frequency of hclk from 125mhz to 100mhz. 2 . modify some thermal information in section 5.1.7.
AX88180 47 asix electronics corporation 4f, no.8, hsin ann rd., hsinchu science park, hsinchu, taiwan, r.o.c. tel: +886-3-5799500 fax: +886-3-5799558 email: support@asix.com.tw web: http://www.asix.com.tw

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